XOR-based scrambler/descrambler for SSD communication protocols
US10121013B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.