Nonvolatile memories and reading methods thereof
US10121548B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 16, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Nov 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory includes a first array bank coupled to a first bit-line, a second array bank coupled to a second bit-line, a pre-charging circuit, a first selection circuit, a second selection circuit, and a sense amplifier. An address enable signal sent to the first selection circuit controls whether the pre-charging circuit needs to pre-charge the first bit-line and the second bit-line. The sense amplifier is configured to compare a first voltage from the first output terminal of the pre-charging circuit with a second voltage from the second output terminal of the pre-charging circuit to obtain a result indicating data information stored in the first array bank or in the second array bank. The second selection circuit is configured to connect a reference current to the first input terminal or the second input terminal of the sense amplifier based on a first word-line signal and a second word-line signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.