Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays
US10121553B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Aug 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.