Manufacturing method of top gate thin-film transistor
US10121883B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 15, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Jan 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/428
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a manufacturing method of a top gate thin-film transistor, which includes forming a reducing metal layer on an oxide semiconductor layer and applying laser annealing to reduce the oxide semiconductor layer that is covered with the reducing metal layer to conductors to respectively form a source contact zone and a drain contact zone, such that the source contact zone and the drain contact zone that have been reduced to conductors are used to respectively contact a source electrode and a drain electrode thereby greatly reducing the contact resistance of the source electrode and the drain electrode and improving the performance of a top gate thin-film transistor. The manufacturing process is simple.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.