Active gate clamping for inverter switching devices with enhanced common source inductance
US10122294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2016 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Mar 19, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An inverter phase leg has upper and lower gate drive circuits supplying gate drive signals to upper and lower transistors. Each gate drive circuit includes an active clamp for selectively deactivating the upper and lower transistors. The transistors are comprised of semiconductor devices, each having respective gate, source, and emitter terminals. Each emitter terminal is connected to a respective output electrode structured to enhance a common source inductance between the respective gate and emitter terminals. Each emitter terminal is further connected to a respective Kelvin emitter electrode substantially bypassing the respective output electrode. Each respective active clamp is connected between the respective gate terminal and Kelvin emitter electrode so that the active clamping function remains effective in the presence of the enhanced common source inductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.