Auto-bias circuit for stacked FET power amplifier
US10122333B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to circuitry including an auto-bias circuit for a stacked FET power amplifier. The auto-bias circuit includes a dividing circuit and an averaging circuit. The dividing circuit is configured to receive a control signal with a control voltage and provide a first pre-gate signal having a first pre-gate voltage that corresponds to a fraction of the control voltage. The averaging circuit is configured to receive the control signal and a supply signal with a supply voltage and provide a second pre-gate signal having a second pre-gate voltage that corresponds to a fraction of a sum of the control voltage and the supply voltage. The stacked power amplifier includes a first FET in series with a second FET. The first FET receives a first gate signal derived from the first pre-gate signal. The second FET receives a second gate signal derived from the second pre-gate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.