Patent · US Active

Phase detector in a delay locked loop

US10122526B2 · kind B2 · utility

0Cited by

5References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Fangxing Wei · Folsom, US
Dan Shi · Folsom, US
Michael J. Allen · Rescue, US

Key dates

Filing date	Apr 1, 2017
Grant date	Nov 6, 2018
Priority date	—
Expiry date	Apr 1, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/04
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase detector can include a first latch operable to set a first latch output depending on a lead-lag status between the reference clock and the feedback clock. The phase detector can include a second latch that loads the lead-lag status when the reference clock and the feedback clock produce clock signals in a high state. The phase detector can include a third latch that loads the lead-lag status from the second latch when the reference clock and the feedback clock produce clock signals in a low state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.