Output queue latency behavior for input queue based device
US10122645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2012 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | Feb 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one implementation, an input queue switch provides latency fairness across multiple input ports and multiple output ports. In one embodiment, each input port maintains a virtual output queue for each associate output port. The virtual output queues across multiple inputs are aggregated for each specific output port. The sum of the lengths of the virtual output queues is compared to a threshold, and based on the comparison, feedback may be generated to control the operation of the input port for subsequent packets. The feedback may instruct the input port to stop buffering or drop packets destined for the output port with the sum of the lengths of the virtual output queues associated to the specific output port that exceeds the threshold. In another embodiment, each packet has an arrival timestamp, and a virtual output queue having the oldest timestamp is selected first to dequeue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.