Input impedance biasing
US10123117B1 · kind B1 · utility
0Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2017 |
| Grant date | Nov 6, 2018 |
| Priority date | — |
| Expiry date | May 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2201/003
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Input impedance biasing may be improved with an ultra-high-input-impedance biasing circuit having low temperature variation. The impedance biasing circuit may include a first transistor coupled to a first power supply and a second transistor coupled to a second power supply. A gate of the first transistor may be coupled to a gate of the second transistor at an intermediate bias node. The first transistor and the second transistor may provide a selected DC impedance at the intermediate bias node. The impedance may be used to provide low-pass and or high-pass filtering of audio signals and/or noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.