Operation of a multi-slice processor implementing adaptive failure state capture
US10127121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2016 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Nov 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3055
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.