Method for the coexistence of software having different safety levels in a multicore processor system
US10127161B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2015 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for the coexistence of software having different safety levels in a multicore processor which has at least two processor cores (2, 3). A memory range (4, 5) is associated with each processor core (2, 3) and a plurality of software (SW1, SW2) is processed on one of the processor cores (2, 3) having a predefined safety level. The plurality of software (SW1, SW2) is processed having a predefined safety level only on the processor core (2, 3) with which the same safety level is associated, in which during the processing of the plurality of software (SW1, SW2), the processor core (2, 3) accesses only the protected memory range (4, 5) which is permanently associated with this processor core (2, 3).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.