Circuit design layout in multiple synchronous representations
US10127343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This application discloses a computing system implementing tools and mechanisms to synchronize multiple layouts for a circuit design during the layout process. The tools and mechanisms can implement multiple communicating kernels, each to manage at least one of the layouts. In response to an alteration of one of the layouts, the kernels can communicate with each other, so that the kernel corresponding to the unaltered layout can automatically augment corresponding layouts for the circuit design to synchronize with the altered layout. At least one of the layouts can include a 3-dimensional layout representation of the circuit design, the tools and mechanisms can perform 3-dimensional design rule checking based on mechanical constraints and 3-dimensional solid component models in response to alterations to a 2-dimensional layout representation of the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.