Array substrate, its manufacturing method, and display device
US10127855B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 9, 2014 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Dec 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1315
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The array substrate according to the present disclosure may include within its fanout region a plurality of signal transmission lines for transmitting signals between a driver chip and a display region of the array substrate, and each signal transmission line may correspond to one data transmission channel. The array substrate may further include at least one impedance balancing line arranged corresponding to a signal transmission line in the plurality of signal transmission lines, wherein the impedance balancing line is electrically connected to the signal transmission line, so that a difference between impedances of different data transmission channels within the fanout region meets a first predetermined condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.