Circuitry for ferroelectric FET-based dynamic random access memory and non-volatile memory
US10127964B2 · kind B2 · utility
8Cited by
9References
15Claims
0Family size
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Key dates
| Filing date | Jul 2, 2015 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jul 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.