Method of conditioning an etch chamber for contaminant free etching of a semiconductor device
US10128133B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/022
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An etching tool that includes an interior chamber is provided. A plurality of type III-V semiconductor wafers is provided. A process cycle is performed for each one of the type III-V semiconductor wafers in the plurality. The process cycle includes performing a preliminary contamination control process. The process cycle further includes inserting one of the type III-V semiconductor wafers into the interior chamber. The process cycle further includes etching type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber. The process cycle further includes removing the type III-V semiconductor wafer that is present in the interior chamber. The preliminary contamination control process includes forming a carbon containing protective material that completely covers exposed surfaces of the interior chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.