Semiconductor device with fin field effect transistors having different separation regions between fins in NMOS and PMOS regions
US10128243B2 · kind B2 · utility
30Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Dec 1, 2015 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Dec 5, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A semiconductor device includes a substrate with a NMOS region and a PMOS region, a device isolation layer on the substrate to define active fins, and gate patterns on the substrate to have a length direction crossing the active fins, wherein the device isolation layer includes diffusion brake regions between respective pairs of the active fins, the diffusion brake regions being disposed adjacent to each other in a width direction of the gate patterns, and wherein a width of the diffusion brake region in the NMOS region is different from a width of the diffusion brake region in the PMOS region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.