Relay protection method and apparatus against LC parallel circuit detuning faults
US10128650B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 8, 2015 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Oct 23, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E60/60
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A relay protection method against LC parallel circuit detuning faults comprises the steps of: a relay protection device samples a current of a parallel LC, that is, a reactor and a capacitor, and samples a total current flowing through the whole LC; convert the current of the reactor into a current of an equivalent capacitor; calculate amplitudes of the current of the equivalent capacitor and a current of a realistic capacitor and calculate an amplitude of the total current flowing through the LC; calculate a current amplitude ratio of the equivalent capacitor to the realistic capacitor; and when the amplitude of the total current flowing through the LC is large enough, send an alarm signal or a trip after a setting time delay if the current ratio exceeds a preset upper and lower limit range. Also provided is a corresponding relay protection device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.