Integrated circuit calibration architecture
US10128963B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Jun 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/19
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A calibration architecture that enables accurate calibration of radio frequency (RF) integrated circuits (ICs) chips used in transceiver RF systems in a relatively simple testing environment. Embodiments of the invention include one or more on-chip switchable internal calibration paths that enable direct coupling of a portion of the on-chip circuit to an RF test system while isolating other circuitry on the chip. Periodic self-calibration of an RF IC can be performed after initial factory calibration, so that adjustments in desired performance parameters can be made while such an IC is embedded within a final system, and/or to take into account component degradation due to age or other factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.