Data serializer
US10129016B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Nov 13, 2018 |
| Priority date | — |
| Expiry date | Feb 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.