Semiconductor chip, test system, and method of testing the semiconductor chip
US10132865B2 · kind B2 · utility
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18References
22Claims
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Key dates
| Filing date | Jun 1, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Jun 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31708
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.