Dynamic partitioning of processing hardware
US10133504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of partitioning host processing system resources is provided. An integrated circuit device having a plurality of processors or processing cores and a number of interfaces is portioned at boot into different hardware partitions based on the application needs of the host processing system. The technology provides a non-transitory memory storage including instructions; and a plurality of processors in communication with the memory. The integrated circuit device also includes a plurality of communication interfaces in communication with the processors. At least one of the plurality of processors executes instructions to configure a subset of the plurality of processors to a first hardware partition, and configure a different subset of the plurality of processors and at least one of the plurality of communication interfaces to a second hardware partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.