Device including a single wire interface and a data processing system having the same
US10133692B2 · kind B2 · utility
2Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Jan 20, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.