Guided defect detection of integrated circuits
US10133838B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | May 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for detecting defects of integrated circuits have been provided. The method comprises generating process sensitive patterns of an integrated circuit, scanning the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determining care areas of the integrated circuit using the process condition parameters, and scanning the care areas using the high-resolution system to detect at least one defect of the integrated circuit. The system comprises a processor and a memory with instructions executable by the processor to generate process sensitive patterns of an integrated circuit, scan the process sensitive patterns using a high-resolution system to provide process condition parameters of the integrated circuit, determine care areas of the integrated circuit using the process condition parameters, and scan the care areas using the high-resolution system to detect at least one defect of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.