Adiabatic phase gates in parity-based quantum computers
US10133984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Aug 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N99/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example methods and mechanisms are described herein for implementing and adiabatically operating a topological quantum computing (TQC) phase gate that complements the existing Clifford operations, and thereby allows universal quantum computation with Majorana systems. Further embodiments include a testing system for the phase gate that is feasible with Majorana zero modes and demonstrates violations of the CHSH-Bell inequality. Further, the design used for the testing of the inequality leads directly to a practical platforms for performing universal TQC with Majorana wires in which explicit braiding need never occur. Thus, certain embodiments of the disclosed technology involve three synergistically connected aspects of anyonic TQC the context of the currently active area of using MZMs for topological quantum computation): a practical phase gate for universal topological quantum computation using MZMs, a precise protocol (using CHSH inequality) for testing that the desired gate operation has been achieved, and bypassing the necessity of MZM braiding (and so avoiding, e.g., problems of nonadiabaticity in the braids).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.