Floating gate architecture for deep neural network application
US10134472B1 · kind B1 · utility
13Cited by
2References
20Claims
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Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive processing unit (RPU) circuit for use in a neural network application includes at least one floating gate storage device, the floating gate storage device including a floating gate, a control gate and an inject/erase gate. The RPU circuit further includes a feedback circuit connected with the floating gate storage device. The feedback circuit is configured to maintain a substantially constant floating gate potential of the floating gate storage device during an update mode of operation of the RPU circuit, and is disabled during a readout mode of operation of the RPU circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.