Memory device including a redundancy column and a redundancy peripheral logic circuit
US10134486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Sep 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array including a plurality of memory cells arranged in a plurality of columns including a normal column and a redundancy column for repairing the normal column, a plurality of peripheral logic circuits including a normal peripheral logic circuit and a redundancy peripheral logic circuit for repairing the normal peripheral logic circuit, and a first path selection logic circuit configured to form first paths between the plurality of columns and the plurality of peripheral logic circuits, based on at least one defect from among a defect in at least one of the plurality of columns or a defect in at least one of the plurality of peripheral logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.