Semiconductor memory device and memory system including the same
US10134487B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 15, 2015 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Sep 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.