Integrated circuit chip protection against physical and/or electrical alterations
US10135239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip and a method for protecting the integrated circuit chip against physical and/or electrical alterations are disclosed. The chip comprises at least one semiconductor layer including semiconductor components and conductive tracks, at least one layer formed by a first type of conductive tracks extending over all or part of a surface of the chip and at least one second type of conductive track connected to at least one detection circuit configured to detect an alteration of the at least one second type of conductive track. The chip is characterized in that the at least one first type of conductive track is mixed within the at least one second type of conductive track, the material and the layout of at least one second type of conductive track being indiscernible, by an observation device, from the material and the layout of the at least one first type of conductive track.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.