Reset circuit and electronic device
US10135436B2 · kind B2 · utility
0Cited by
4References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 29, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Mar 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset circuit includes a detect circuit, a maintain circuit and an output circuit. The detect circuit and the maintain circuit are coupled to the output circuit, wherein the detect circuit is arranged to detect at least an input power provided to a loading, and make the output circuit output a reset signal when a voltage of the input power goes into an abnormal state, and the maintain circuit is arranged to stop the output circuit from outputting the reset signal when the loading is in a standby state. The reset circuit is applied within an electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.