Oversampling noise-shaping successive approximation ADC
US10135454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2015 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Dec 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation Analog to Digital Converter (ADC), comprising: a sample and hold device arranged to sample and hold an input signal at the beginning of a conversion cycle; a successive approximation register that sequentially builds up a digital output from its most significant bit to its least significant bit; a digital to analog converter that outputs a signal based on the output of the successive approximation register; a comparator that compares the output of the digital to analog converter with an output of the sample and hold device and supplies its output to the successive approximation register; and a residual signal storage device arranged to store the residual signal at the end of a conversion cycle; and wherein the successive approximation ADC is arranged to add the stored residual signal from the residual signal storage device to the input signal stored on the sample and hold device at the start of each conversion cycle. After each ADC full conversion by the SAR, the analog conversion of the digital output is as close to the original input signal as the resolution will allow. However there remains the residual part of the input signal that is smaller than wha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.