Digitally calibrated successive approximation register analog-to-digital converter
US10135455B2 · kind B2 · utility
1Cited by
8References
17Claims
0Family size
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Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.