Clock recovery method, device and system and computer storage medium
US10135543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03038
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock recovery method is provided. The method has the following operations: performing clock balance pre-filtering on an input time/frequency domain signal according to a self-adaptive balance coefficient input currently, to obtain a balance pre-filtering signal; according to the balance pre-filtering signal, acquiring a phase error of the input time/frequency domain signal; and performing phase adjustment on the input time/frequency domain signal according to the phase error, and outputting a new self-adaptive balance coefficient after self-adaptive balance processing is performed on the phase-adjusted time/frequency domain signal. A clock recovery device and system and a non-transitory computer-readable storage medium are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.