Network-based computational accelerator
US10135739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Nov 20, 2018 |
| Priority date | — |
| Expiry date | Dec 1, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing device includes a first packet communication interface for communication with at least one host processor via a network interface controller (NIC) and a second packet communication interface for communication with a packet data network. A memory holds a flow state table containing context information with respect to multiple packet flows conveyed between the host processor and the network via the first and second interfaces packet communication interfaces. Acceleration logic, coupled between the first and second packet communication interfaces, performs computational operations on payloads of packets in the multiple packet flows using the context information in the flow state table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.