Apparatus for power consumption reduction in electronic circuitry and associated methods
US10139896B2 · kind B2 · utility
1Cited by
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15Claims
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Assignee
Inventors
Key dates
| Filing date | Jul 8, 2015 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Apr 29, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a circuit that has a normal mode of operation and a low-power mode of operation. The circuit consumes more power in the normal mode of operation than in the low-power mode of operation. The apparatus further includes a power-supply circuit. The power-supply circuit provides a normal supply voltage to the circuit in the normal mode of operation. The power-supply circuit includes a non-linear circuit to provide a compressed supply voltage to the circuit in the low-power mode of operation, wherein the normal supply voltage is greater than the compressed supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.