Computer-implementable method for use with a surge arrester
US10140397B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Aug 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implementable method for simulating the electrical behavior of a surge arrester comprises providing a model of the surge arrester with a switchable current path between an anode and a cathode of the surge arrester, wherein the current path comprises a controllable voltage source. The current path is switched into the conducting or blocked state depending on a determined value of a voltage rise of an input voltage present between the anode and the cathode and a determined level of a response voltage. A level of the voltage of the controllable voltage source is set depending on a level of a current flowing in the current path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.