Representing a routing strip in an integrated circuit design using a digit pattern
US10140410B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Feb 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein provide techniques for representing a routing strip in an integrated circuit design using a digit pattern. According to certain aspects, the techniques include methods to display overlapped routing strips of an integrated circuit design when there are ten or more metal layers in the integrated circuit design. According to additional or alternative aspects, the techniques include methods to generate a texture pattern for displaying routing strips in which layer identification and layer direction of each routing strip can be easily discerned. According to further additional or alternative aspects, the techniques include methods to cause texture patterns for displaying routing strips to stagger with respect to each other when the routing strips are overlapped in a display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.