Hardware-accelerated resource tiling
US10140680B2 · kind B2 · utility
1Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2013 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Jun 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a graphics processing unit 170 may support a logical resource using a physical tile pool 350 for sparse data sets. The graphics processing unit 170 may allocate a physical memory allocation into a primary physical tile pool 350. The graphics processing unit 170 may define a mapping for a logical tile set 300 for a logical resource. The graphics processing unit 170 may selectively map a primary logical tile 320 of the logical tile set 300 to a primary physical tile 360 of the primary physical tile pool 350.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.