Shift register, a gate line driving circuit, an array substrate and a display apparatus
US10140910B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 10, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Jan 31, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a shift register, a gate line driving circuit, an array substrate and a display apparatus. The shift register comprises: an inputting circuit for controlling a potential of a pulling up node (PU); a pulling down driving circuit for controlling the potentials of the PU and a pulling down node to be different; a resetting circuit for pulling down the PU and a signal outputting terminal (Output); a first outputting circuit for pulling down the Output; a second outputting terminal for outputting a signal from a clock signal terminal via the Output; a controlling circuit for connecting the second outputting circuit with the PU when the PU is at a high level and pulling the first terminal of the second outputting circuit down to a potential as twice as the potential of the low level signal terminal when the PU is at a low level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.