Shift register unit, gate drive circuit and display device
US10140913B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 18, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Oct 18, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The shift register unit comprises: a gate drive signal output terminal, a first clock signal input terminal, a second clock signal input terminal, a low level input terminal, a pull-up control unit, a pull-down unit, a pull-down node control unit and a pull-down control node control unit. In a pull-down holding phase of a display period, a first clock signal input through the first clock signal input terminal and a second clock signal input through the second clock signal input terminal have opposite phases. When the first clock signal has a high level, the pull-down control node control unit controls the pull-down control node to be connected to the first clock signal input terminal. When the second clock signal has a high level, the pull-down control node control unit controls the pull-down control node to be connected to the low level input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.