Chip and electronic device
US10141250B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Mar 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points are laid out in the substrate. Solder joints in a solder joint matrix at a bottom of the substrate include a first solder joint group and a second solder joint group that are arranged along two parallel lines. Substrate cables connected to solder joints in the first solder joint group have an equal length. Substrate cables connected to solder joints in the second solder joint group have an equal length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.