Thin-film-transistor (TFT) array panel with stress elimination layer and method of manufacturing the same
US10141341B2 · kind B2 · utility
0Cited by
1References
6Claims
0Family size
Assignees
Inventor
Key dates
| Filing date | Nov 24, 2015 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Nov 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K2102/311
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides a thin-film-transistor (TFT) array panel and manufacturing method of the same. The TFT array panel comprises a flexible baseplate, a buffer layer, and a display-element layer. The buffer layer is disposed on the flexible baseplate, a stress-elimination portion is disposed on the buffer layer, the stress-elimination portion is used to eliminate a stress of the flexible baseplate; the display-element layer is disposed on the buffer layer. The present invention is able to decrease the stress of the flexible baseplate, to prevent too large of a stress of the flexible baseplate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.