Semiconductor devices including field effect transistors with dummy gates on isolation
US10141400B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | Nov 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes device isolation layer on a substrate to define an active region, a first gate electrode on the active region extending in a first direction parallel to a top surface of the substrate, a second gate electrode on the device isolation layer and spaced apart from the first gate electrode in the first direction, a gate spacer between the first gate electrode and the second gate electrode, and source/drain regions in the active region at opposite sides of the first gate electrode. The source/drain regions are spaced apart from each other in a second direction that is parallel to the top surface of the substrate and crossing the first direction, and, when viewed in a plan view, the first gate electrode is spaced apart from a boundary between the active region and the device isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.