System and method for eliminating gate voltage oscillation in paralleled power semiconductor switches
US10141923B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Nov 27, 2018 |
| Priority date | — |
| Expiry date | May 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04106
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus for eliminating gate voltage oscillation without increasing switching power loss in paralleled power semiconductor switches at high current turn-off. The damping circuit includes a switch for driving voltage and multiple resistors and multiple inductors. The damping circuit includes multiple capacitors connected to the multiple inductors. The damping circuit includes multiple power semiconductor switches that are connected to the multiple inductors at gate terminals. The damping circuit includes multiple gate terminal resistors connected in parallel to the multiple power semiconductor switches at the gate terminals and multiple gate terminal switches connected to the multiple gate terminal resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.