Resolving automated test equipment (ATE) timing constraint violations
US10145893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 25, 2016 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Feb 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2834
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing an integrated circuit device, which involves receiving, by a processor, a test definition indicating a sequence of acts to be performed by an automated test equipment in testing an integrated circuit device. The test definition includes indications of test cycles and timings of events in the cycles. The method includes scanning the received test definition, by the processor, for switch time points for which a timing of events in a first cycle immediately preceding the switch time point is different from a timing of events in a second cycle immediately following the switch time point, determining problematic switch time points for which the combined rest duration from a specific event in the first cycle to a corresponding specific event in the second cycle is shorter than a minimal switch period of the automated test equipment, changing the received test definition by extending a length of the cycles immediately preceding the determined problematic switch time points and providing the changed test definition for testing the integrated circuit device by the automated test equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.