Full chip lithographic mask generation
US10146124B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Feb 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus, and a non-transitory computer readable medium for full chip mask pattern generation include: generating, by a processor, an initial mask image from target polygons, performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels, determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization, generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information, and generating optimized mask patterns based on a localized polygon optimization of the mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.