CMOS subthreshold reference circuit with low power consumption and low temperature drift
US10146238B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jul 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J2207/10
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to μT2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of −40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from μW level to nW level and realize low power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.