Translation address cache for a microprocessor
US10146545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2012 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.