System, method, and controller for supplying address and command signals after a chip select signal
US10147477B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One controller for controlling operation of a memory device includes an output circuit configured to supply a chip select signal, an address signal, a command signal, and a clock signal to the memory device, and a data processing circuit configured to process read data and write data through a data terminal based on the chip select signal, the address signal, the command signal, and the clock signal supplied by the output circuit. The controller is configured to supply the address signal and the command signal to the memory device a predetermined duration after the output circuit supplies the chip select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.