Transistor with buried P+ and source contact
US10147801B2 · kind B2 · utility
0Cited by
13References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jan 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.