Low noise amplifier circuit
US10148237B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2017 |
| Grant date | Dec 4, 2018 |
| Priority date | — |
| Expiry date | Jan 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45596
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit comprising an input block having a first chopper providing a chopped voltage signal, a first transconductance converting said chopped voltage signal into a chopped current signal, a second chopper providing a demodulated current signal, a current integrator having an integrating capacitor providing a continuous-time signal, a first feedback path comprising: a sample-and-hold block and a first feedback block, the first feedback path providing a proportional feedback signal upstream of the current integrator. The amplification factor is at least 2. Charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period. Each chopper operates at a chopping frequency. The sample-and-hold-block operates at a sampling frequency equal to an integer times the chopping frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.